A low clock swing, power saving and generic technology based D flip-flop with single power supply

A low power, low clock swing D flip-flop (DFF) based on C²MOS (Clocked CMOS) and sense amplifier (SA) is proposed in this paper. This DFF is extensively applicable as it utilizes generic CMOS technology and needs no additional power supply specially for the clock sub-circuit. Simulation result shows that the average leakage power and dynamic power of this DFF are reduced by 78.73% and 8.74% respectively, with the delay slightly smaller, with the clock swing as low as 658 mV (under 1.8 V supply).