DocumentCode :
2567535
Title :
A Task-level Hierarchical Memory Model For System Synthesis Of Multiprocessors
Author :
Li, Yanbing ; Wolf, Wayne
Author_Institution :
Dept. of EE, Princeton University
fYear :
1997
fDate :
9-13 June 1997
Firstpage :
153
Lastpage :
156
Keywords :
Computer architecture; Modems; Multiprocessing systems; Partitioning algorithms; Permission; Processor scheduling; Real time systems; Reduced instruction set computing; Scheduling algorithm; Software algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
ISSN :
0738-100X
Print_ISBN :
0-7803-4093-0
Type :
conf
DOI :
10.1109/DAC.1997.597135
Filename :
597135
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2567535
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