An FPGA configuration circuit used for fast and partial configuration

Author

Wang, Yabin ; Wang, Yuan ; Lai, Jinmei

Author_Institution

Fudan Univ., Shanghai

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

157

Lastpage

160

Abstract

An improved architecture used for FPGA´s fast and partial configuration is proposed. It is designed based on a 32 bits wide data bus, which can be controlled by a set of instructions. A partial control register and an address decoding logic are added in this design. Multiple configuration interfaces could be connected in this architecture, making hardware updating fast and convenient. Comparing with Virtex Series FPGA´s configuration architecture, produced by Xilinx Corp., which only can configure memory cells by frame, this new architecture could configure any single memory cell in FPGA, offering more flexible configuration operations.

Keywords

field programmable gate arrays; FPGA configuration circuit; Virtex Series FPGA configuration architecture; Xilinx Corp; address decoding logic; data bus; memory cells; partial configuration; partial control register; Art; Decoding; Field programmable gate arrays; Flexible printed circuits; Hardware; Logic design; Microelectronics; Random access memory; Read-write memory; Registers; Data Configuration; Multiple Data Bus; Partial Configuration; Xilinx Virtex Series FPGA;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1132-0

Electronic_ISBN

978-1-4244-1132-0

Type

conf

DOI

10.1109/ICASIC.2007.4415591

Filename

4415591