Design and implementation of a high-speed reconfigurable multiplier

On the basis of analyzing the theory of multiplication operation in block ciphers and modular multiplication algorithms of different operation width, this paper present a high-speed reconfigurable multiplier, which can be reconfigured to perform 16-bit, 32-bit multiplication and modulo 2¹⁶+1 multiplication operation, and then optimize each critical block. The design is realized using Altera´s FPGA. Synthesis, placement and routing of reconfigurable multiplier have accomplished on 0.18 mum SMIC technology. The result proves that the propagation time of the critical path is 2.84 ns. The reconfigurable multiplier is able to achieve relatively high performance in the block cipher algorithms processing.