Title :
Montgomery multiplier based on secondary booth encoded algorithm
Author :
Yan, Xiaodong ; Li, Shuguo
Author_Institution :
Tsinghua Univ., Beijing
Abstract :
This paper describes a high-speed Montgomery multiplier based on pipeline large-scale multiplier. It uses secondary booth encoded algorithm for cutting down the number of partial products and adjusting the data-path to get shorter critical path. An ASIC implementation in 0.18 um CMOS standard cell technology can perform 256-bit modular multiplication in 15 ns under 200 MHz clock frequency. The design can be employed in advanced cryptographic system chips such as RSA or ECC chip.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; cryptography; encoding; multiplying circuits; pipeline arithmetic; ASIC implementation; CMOS standard cell technology; Montgomery multiplier; cryptographic system chips; pipeline large-scale multiplier; secondary booth encoded algorithm; Application specific integrated circuits; Authentication; CMOS technology; Clocks; Computer architecture; Elliptic curve cryptography; Frequency; Large-scale systems; Pipelines; Public key cryptography;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415601
