Analysis and software implementation of a robust synchronizing circuit PLL circuit

This paper presents the analysis and software implementation of a robust synchronizing circuit - PLL circuit - designed for using in the controller of active power line conditioners. The basic problem consists in designing a PLL circuit that can track accurately and continuously the positive-sequence component at the fundamental frequency and its phase angle, even when the system voltage of the bus, to which the active power line conditioner is connected, is distorted and/or unbalanced. The fundaments of the PLL circuit are discussed. It is shown that the PLL can fail in tracking the system voltage during the startup, under some adverse conditions. Moreover, it is shown that oscillations caused by the presence of sub-harmonics can be very critical and can pull the stable point of operation synchronized to that sub-harmonic frequency. Oscillations at the reference input are also discussed, and the solution of this problem is presented. Finally, experimental and simulation results are shown and compared.