DocumentCode :
2567942
Title :
Trends in high speed ADC design
Author :
Matsuzawa, Akira
Author_Institution :
Tokyo Inst. of Technol., Tokyo
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
245
Lastpage :
248
Abstract :
This paper discusses trends in the design of high speed ADCs. Technology scaling has enabled an increased conversion rate; however, it now also leads to difficulties with increased resolution, with the SNR, and with decreased power consumption, especially for higher resolutions. New converter design challenges are needed. One strong trend in the design of ADCs is to omit operational amplifiers (OpAmps), which used to form the basis of modern ADCs but are now no longer useful. Comparator based ADCs, such as successive approximation ADCs, sub-ranging ADCs, or pipelined ADCs which all are used comparator-based design instead of conventional OpAmp-based design, become attractive as future high speed ADC architectures.
Keywords :
analogue-digital conversion; comparators (circuits); operational amplifiers; comparator-based design; conversion rate; converter design; high speed ADC design; operational amplifiers; power consumption; technology scaling; Analog circuits; CMOS analog integrated circuits; CMOS technology; Digital systems; Dynamic range; Energy consumption; Operational amplifiers; Pipelines; Sampling methods; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415613
Filename :
4415613
Link To Document :
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