• DocumentCode
    2567956
  • Title

    A 10b 50MS/s pipelined ADC with opamp current reuse

  • Author

    Seung-Tak Ryu ; Bang-Sup Song ; Bacrania, K.

  • Author_Institution
    California Univ., San Diego, CA
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    792
  • Lastpage
    801
  • Abstract
    Power-saving techniques such as opamp current reuse and capacitive level shift reduce the power consumption of a 10b pipelined ADC to 220muW/MHz. A 50MS/S prototype in 0.18mum CMOS consumes 18mW (11mW for analog) at 1.8V and occupies 1.1times1.3mm2. The measured ENOB of the ADC is 9.2b (8.8b) for a 1MHz (20MHz) input
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; operational amplifiers; 0.18 micron; 1 MHz; 1.8 V; 10 bit; 11 mW; 18 mW; 20 MHz; CMOS process; capacitive level shift; opamp current reuse; pipelined ADC; power saving; Capacitors; Clocks; Delay; Energy consumption; MOS devices; Output feedback; Sampling methods; Switches; Turning; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696119
  • Filename
    1696119
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2567956