DocumentCode
2568034
Title
A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13/spl mu/m CMOS
Author
Bogner, P. ; Kuttner, F. ; Kropf, Carsten ; Hartig, T. ; Burian, M. ; Eul, H.
Author_Institution
Infineon, Villach
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
832
Lastpage
841
Abstract
A 14b multi-bit-per-stage pipelined ADC is implemented in a 0.13mum digital CMOS process. The gain and matching errors of the analog circuitry are compensated by a digital calibration scheme that allows the usage of a low-gain op-amp. A low power consumption has been reached by introducing a charge compensation scheme
Keywords
CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; operational amplifiers; 0.13 micron; 14 bit; charge compensation; digital CMOS process; gain errors; matching errors; operational amplifiers; self-calibrated pipelined ADC; CMOS process; CMOS technology; Calibration; Capacitors; Circuits; Energy consumption; High-resolution imaging; Intersymbol interference; Low voltage; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696123
Filename
1696123
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