Title :
A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders
Author :
Chan, Chi-Hong ; Chan, Cheong-Fat ; Choy, Chiu-Sing ; Pun, Kong-Pang
Author_Institution :
Chinese Univ. of Hong Kong, Shatin
Abstract :
This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.
Keywords :
CMOS integrated circuits; adders; analogue-digital conversion; error correction; 6-digit RSD analog to quaternary converter; CMOS current mode quaternary adders; SFDR; SNDR; THD; error correction algorithm; frequency 50 MHz; pipelined architecture; redundant signed digit; size 0.35 mum; voltage 2.5 V; Adders; CMOS logic circuits; CMOS process; CMOS technology; Error correction; Integrated circuit interconnections; Modems; Quantization; Sampling methods; Voltage;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415623
