DocumentCode
2568142
Title
A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation
Author
Wei, D.C. ; Huang, Yi-Pai ; Garlepp, B.W. ; Hein, Joachim
Author_Institution
Silicon Labs., Austin, TX
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
884
Lastpage
893
Abstract
A single-chip jitter-cleaning PLL with hitless switching is presented. By utilizing the mostly-digital phase build-out technique, the steady-state output phase step after switching is bounded within 200ps. At the loop bandwidth of 800Hz, the maximum output phase transient slope is <4.5ns/ms. The jitter generation is 0.8ps in the OC48 band and 0.4ps in OC192 band. The 16.32mm2 chip is fabricated in a 0.25mum standard CMOS process and consumes 350mW at 3.3V
Keywords
SONET; clocks; digital signal processing chips; jitter; phase locked loops; voltage-controlled oscillators; 0.25 micron; 3.3 V; 350 mW; 800 Hz; CMOS process; OC192 band; OC48 band; SDH; SONET; clock generation; digital phase build-out technique; hitless switching; jitter-cleaning PLL; Bandwidth; Clocks; Jitter; Phase frequency detector; Phase locked loops; Phase noise; SONET; Switches; Synchronous digital hierarchy; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696129
Filename
1696129
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