1.25Gb/s low jitter dual-loop clock and data recovery circuit

The design of 1.25 Gb/s low jitter frequency-aided dual-loop CMOS clock and data recovery circuit (CDR) applied in SerDes (Serializer&Deserializer) transceiver for Gigabit Ethernet is described. The FLL circuit is adopted to enhance the tracking range of CDR. A special phase detector based on three-state PFD is proposed here to extract clock information from 1.25 Gb/s NRZ data stream, and drive a three-staged current-starving ring oscillator to generate the low jitter 1.25 GHz clock needed in the receiver of SerDes. The CDR circuit is fabricated in TSMC 0.35 mum 2P3M 3.3 V/5 V mixed signal CMOS technology. The measured result shows a good jitter performance of the CDR output clock: the 1sigma RJ is 0.0009UI, and the TJ is 0.058U.