DocumentCode
2568179
Title
Design a 4GHz PLL for wireless receiver
Author
Wang, Yunfeng ; Ye, Qing ; Man, Jiahan ; Fan, Jun ; Ye, Tianchun
Author_Institution
Chinese Acad. of Sci., Beijing
fYear
2007
fDate
22-25 Oct. 2007
Firstpage
315
Lastpage
318
Abstract
:This paper presents the design of a 4 GHz PLL used in wireless receiver. The Verilog-A models are used in behavioral level simulation and in post-layout simulation. The design is based on SMIC 0.18 um 1P6M CMOS RF process. The settling time is 19us and the reference spur is 42.2 dB, the phase noise of VCO is -115 dBc/Hz@lMHz, the power dissipation of the PLL is 36 mW.
Keywords
CMOS integrated circuits; phase locked loops; radio receivers; voltage-controlled oscillators; CMOS RF process; PLL; VCO; Verilog-A model; frequency 4 GHz; phase locked loop; size 0.18 mum; voltage controlled oscillator; wireless receiver; Charge pumps; Circuit simulation; Clocks; Hardware design languages; Low pass filters; Phase frequency detector; Phase locked loops; Semiconductor device modeling; Transfer functions; Voltage-controlled oscillators; PLL; Verilog-A; behavioral level simulation; reference spur;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4244-1132-0
Electronic_ISBN
978-1-4244-1132-0
Type
conf
DOI
10.1109/ICASIC.2007.4415630
Filename
4415630
Link To Document