Efficient Design of Shift Registers Using Reversible Logic

Reversible shift registers are required to construct reversible memory circuits. This paper presents novel designs of reversible shift registers such as serial-in serial-out (SISO), serial-in parallel-out (SIPO), parallel-in serial-out (PISO), parallel-in parallel-out (PIPO) and universal shift registers. In order to show the efficiency, lower bounds of the proposed designs are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement shift registers (except SISO). Appropriate theorems and lemmas are presented to clarify the proposed designs. The contribution of this paper will engender a new thread of research in the field of reversible sequential circuits.