A Programmable Spread Spectrum Clock Generation

Author

Jiapeng Zheng ; Peng Ren ; Chien Chun Shao ; Yi Yang ; Juncheng Wang ; Wei Li ; Chinglong Lin ; Yuhua Cheng ; Yangyuan Wang

Author_Institution

SMIC, Shanghai

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

337

Lastpage

339

Abstract

In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. The proposed SSCG with a third-order sigma-delta modulator can generate clocks with center spread ratios of 0.25%, 1%, 1.75%, 2.5%, 3.5%, 5% and down spread ratios of 0.5%, 2%, 3.5%, 5%, 7%, 10%. The SSCG is implemented on a chip using SMIC 0.13 um CMOS process. Measurements show that 11.31 dB attenuation of the EMI at 80 MHz with down spread ratio of 10% and 12.98 dB attenuation at 133.3 M with center spread ratio of 5% can be achieved which have a good agreement with the theoretical calculations.

Keywords

CMOS digital integrated circuits; clocks; electromagnetic interference; phase locked loops; programmable circuits; sigma-delta modulation; CMOS process; EMI; PLL; SSCG; center spread ratio; down spread ratio; programmable spread spectrum clock generation; size 0.13 mum; third-order sigma-delta modulator; triangular modulation; Attenuation; Clocks; Delta-sigma modulation; Digital modulation; Frequency; Low pass filters; Modulation coding; Phase locked loops; Semiconductor device measurement; Spread spectrum communication;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1131-3

Type

conf

DOI

10.1109/ICASIC.2007.4415635

Filename

4415635