Title :
A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25/spl mu/m CMOS
Author :
De Cam, D. ; Petra, Nicola ; Strollo, Antonio Giuseppe Maria
Author_Institution :
Naples Univ.
Abstract :
Multipartite table methods are used in the implementation of a direct digital frequency synthesizer. Two quadrature 13b outputs are produced with a SFDR >90dB and a frequency resolution of 0.15Hz at a 630MHz clock frequency. The 0.25mum CMOS chip occupies 0.063mm2 and dissipates 76mW from a 2.5V supply at 630MHz
Keywords :
CMOS integrated circuits; UHF integrated circuits; direct digital synthesis; 0.25 micron; 13 bit; 2.5 V; 630 MHz; 76 mW; CMOS; direct digital frequency synthesizer; multipartite table; Delay; Feeds; Flip-flops; Frequency synthesizers; Hardware; Interpolation; Power dissipation; Read only memory; Table lookup; Topology;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696139
