DocumentCode
2568505
Title
Hierarchical Agglomerative Clustering Using Graphics Processor with Compute Unified Device Architecture
Author
Shalom, S. A Arul ; Dash, Manoranjan ; Tue, Minh ; Wilson, Nithin
Author_Institution
Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore
fYear
2009
fDate
15-17 May 2009
Firstpage
556
Lastpage
561
Abstract
We explore the use of todaypsilas high-end graphics processing units on desktops to perform hierarchical agglomerative clustering with the compute unified device architecture - CUDA of NVIDIA. Although the advancement in graphics cards has made the gaming industry to flourish,there is a lot more to be gained the field of scientific computing, high performance computing and their applications. Previous works have illustrated considerable speed gains on computing pair wise Euclidean distances between vectors, which is the fundamental operation in hierarchical clustering. We have used CUDA to implement the complete hierarchical agglomerative clustering algorithm and show almost double the speed gain using much cheaper desk top graphics card. In this paper we briefly explain the highly parallel and internally distributed programming structure of CUDA. We explore CUDA capabilities and propose methods to efficiently handle data within the graphics hardware for data intense, data independent, iterative or repetitive general purpose algorithms such as the hierarchical clustering. We achieved results with speed gains of about 30 to 65 times over the CPU implementation using micro array gene expressions.
Keywords
computer graphic equipment; computer graphics; distributed programming; compute unified device architecture; distributed programming structure; graphics processor; hierarchical agglomerative clustering; Clustering algorithms; Computer architecture; Computer industry; Graphics; Hardware; High performance computing; Iterative algorithms; Iterative methods; Parallel programming; Scientific computing; CUDA hierarchical clustering; GPGPU; acceleration of computations; high performance computing; parallel computing;
fLanguage
English
Publisher
ieee
Conference_Titel
2009 International Conference on Signal Processing Systems
Conference_Location
Singapore
Print_ISBN
978-0-7695-3654-5
Type
conf
DOI
10.1109/ICSPS.2009.167
Filename
5166848
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