• DocumentCode
    2568534
  • Title

    An integrated channel noise-based true random number generator

  • Author

    Eberlein, Matthias ; Bakar, Rosnany Abu

  • Author_Institution
    Malaysia Microelectron. Solutions, Cyberjaya
  • fYear
    2007
  • fDate
    22-25 Oct. 2007
  • Firstpage
    391
  • Lastpage
    394
  • Abstract
    The circuit described retrieves true random numbers from CMOS channel noise, suitable for Smart Card applications. The new concept uses MOS transistors in subthreshold and linear region, and applies continuous time offset cancellation. By this technique a high, well defined gain and small area is achieved simultaneously. A two-stage amplifier architecture ensures low sensitivity to supply and substrate noise. The presented solution is simple and does not require tuning. It was implemented in a 0.18 mum SMIC process, consuming only 25 muW with a 1.8 V supply. Good entropy values can be obtained with sampling frequencies up to 5 MHz.
  • Keywords
    CMOS integrated circuits; MOSFET; amplifiers; digital arithmetic; integrated circuit noise; random number generation; CMOS channel noise; MOS transistors; SMIC process; Smart Card application; continuous time offset cancellation; integrated channel noise-based true random number generator; linear region; substrate noise; subthreshold region; two-stage amplifier architecture; Circuits; Entropy; Low-noise amplifiers; MOSFETs; Noise cancellation; Noise generators; Random number generation; Sampling methods; Smart cards; Tuning;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2007. ASICON '07. 7th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4244-1132-0
  • Electronic_ISBN
    978-1-4244-1132-0
  • Type

    conf

  • DOI
    10.1109/ICASIC.2007.4415649
  • Filename
    4415649