A Framework for Modeling Impact of Intrinsic Parameter Fluctuations at Architectural-Level

As the semiconductor process technology continues to scale deeper into the nanometer region, the intrinsic parameter fluctuations will aggressively affect the performance of future microprocessors. Therefore one of the challenge of advanced CMOS manufacturing lies in modeling and simulating the intrinsic parameter fluctuations for accurately assessing the performance and the yield of the corresponding integrated circuits (ICs). To investigate the impact of IPF at architectural-level, a framework to bridge architecture-level and device-level simulation will be presented. In this work, the framework will include intrinsic parameter fluctuation information from UTB-SOI transistors within the 25 nm and 13 nm technology node into architectural-level simulation. The impact of discrete random dopants in the source/drain regions, line edge roughness and body-thickness variations on a microprocessor cache memory system will be presented.