DocumentCode
2568761
Title
Optimum design of a fully differential 12bit 100MS/s sample and hold module with over 77dB SFDR
Author
Liu, Ke ; Yang, Hai-gang
fYear
2007
fDate
22-25 Oct. 2007
Firstpage
442
Lastpage
445
Abstract
A fully differential sample and hold module has been designed for the front-end of a pipeline ADC using 0.35 mum 2P4M CMOS technology with a power supply of 3.3 V. The key design issues include optimization of speed and accuracy. To meet the requirements, a differential flip-around capacitor topology has been used with special care taken in linearization of switches. Gain-boosted OTA with high DC gain and larger bandwidth is designed and optimized. The output of the module can attain over 77dB SFDR, which is suitable for serving as a front-end in a 12bit 100MS/s pipeline ADC.
Keywords
CMOS integrated circuits; amplification; analogue-digital conversion; operational amplifiers; pipeline arithmetic; sample and hold circuits; CMOS technology; SFDR; differential flip-around capacitor topology; gain-boosted OTA; noise figure 77 dB; optimum design; pipeline ADC; power supply; sample and hold module; voltage 3.3 V; word length 12 bit; Bandwidth; CMOS technology; Capacitors; Circuit noise; Design optimization; Feedback; Pipelines; Power dissipation; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4244-1132-0
Electronic_ISBN
978-1-4244-1132-0
Type
conf
DOI
10.1109/ICASIC.2007.4415662
Filename
4415662
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