Data Recovery and Retiming for the Fully Buffered DIMM 4.8Gb/s Serial Links

Author

Partovi, H. ; Walthes, W. ; Ravezzi, L. ; Lindt, P. ; Chokkalingam, S. ; Gopalakrishnan, Kavitha ; Blum, Andrew ; Schumacher, O. ; Andreotti, C. ; Bruennert, M. ; Celli-Urbani, B. ; Friebe, D. ; Koren, Israel ; Verbeck, M. ; Lange, Uwe

Author_Institution

Infineon Technol., San Jose, CA

fYear

2006

fDate

6-9 Feb. 2006

Firstpage

1314

Lastpage

1323

Abstract

Data recovery and retiming of 4.8Gb/s fully buffered DIMM serial links are described. A 2.4GHz retiming FIFO with an integrated insertion MUX is used to minimize the thru-latency. Fabricated in a 0.13mum 1.5V CMOS technology, the chip occupies 9.2 times 4.5mm². Using wide-band CML techniques, the input sensitivity with a minimum eye-opening of 0.35UI, is better than 50mV_p-pat a BER of 10 ^-12

Keywords

CMOS integrated circuits; buffer storage; integrated circuit design; peripheral interfaces; synchronisation; 0.13 micron; 1.5 V; 2.4 Gbit/s; 4.8 Gbit/s; CMOS technology; data recovery and retiming; fully buffered DIMM; integrated insertion MUX; retiming FIFO; serial links; thru-latency minimization; wide-band CML techniques; Circuits; Clocks; Delay; Filters; Random access memory; Repeaters; Signal processing; Standards development; Transmitters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0079-1

Type

conf

DOI

10.1109/ISSCC.2006.1696179

Filename

1696179