DocumentCode
2569238
Title
An Investigation Of Power Delay Trade-offs On Powerpc
Author
Wang, Qi ; Vrudhula, Sarma B K ; Ganguly, Shantanu
Author_Institution
ECE Dept., University of Arizona
fYear
1997
fDate
9-13 June 1997
Firstpage
425
Lastpage
428
Keywords
CMOS logic circuits; Delay estimation; Energy consumption; Logic circuits; Low power electronics; Optimization methods; Packaging; Permission; Power generation; Reflection;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-7803-4093-0
Type
conf
DOI
10.1109/DAC.1997.597185
Filename
597185
Link To Document