Title :
A 2 Gb/s GaAs 128-bit shift register using standard cells with 0.5 mu m WN/sub x/ gate MESFETs
Author :
Kikaura, Y. ; Terada, T. ; Kameyama, A. ; Kawakyu, K. ; Sasaki, T. ; Toyoda, Noriaki
Author_Institution :
Toshiba ULSI Res. Center, Kawasaki, Japan
Abstract :
A 2-Gb/s GaAs 128-bit shift register was designed using standard cells, and was successfully fabricated using an advanced 0.5- mu m WN/sub x/-gate self-alignment MESFET process with a Mg-implanted p-layer under the n-channel. The chip size was 5.05 mm*3.65 mm, in which about 1050 gates were integrated. The yield of fully functional chips over a 3-in. wafer was as high as 20-30%. The chips operated at 2.0-GHz clock frequency with 3.4-W power dissipation.<>
Keywords :
III-V semiconductors; Schottky gate field effect transistors; application specific integrated circuits; field effect integrated circuits; gallium arsenide; integrated logic circuits; shift registers; 0.5 micron; 128 bit; 2 GHz; 2 Gbit/s; 3.4 W; ASIC; GaAs:Mg; III-V semiconductors; Mg-implanted p-layer; WN/sub x/ gate; clock frequency; monolithic IC; n-channel; power dissipation; self-alignment MESFET process; shift register; standard cells; Circuits; Data acquisition; FETs; Frequency; Gallium arsenide; Inverters; MESFETs; Power dissipation; Schottky diodes; Shift registers;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE
Conference_Location :
Nashville, Tennessee, USA
DOI :
10.1109/GAAS.1988.11040
