Title :
124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory
Author :
Yu-Wei Chang ; Hung-Chi Fang ; Chih-Chi Cheng ; Chun-Chia Chen ; Chung-Jr Lian ; Shao-Yi Chien ; Liang-Gee Chen
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
A JPEG2000 codec capable of processing 1920times1080 HD video at 30frames/s is implemented on a 20.1mm2 die with 0.18mum CMOS technology dissipating 345mW at 1.8V and 42MHz. The level-switched schedule eliminates the 192kB tile memory. Hardware sharing between encoder and decoder reduces silicon area by 40%
Keywords :
CMOS integrated circuits; image coding; video codecs; 0.18 micron; 1.8 V; 345 mW; 42 MHz; CMOS technology; HD video; decoder; encoder; hardware sharing; pixel-pipelined motion-JPEG 2000 codec; Bandwidth; Block codes; Codecs; Decoding; Discrete wavelet transforms; Encoding; Processor scheduling; Random access memory; SDRAM; Tiles;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696213
