• DocumentCode
    2569588
  • Title

    A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications

  • Author

    Chang-Hyo Yu ; Kyusik Chung ; Donghyun Kim ; Lee-Sup Kim

  • Author_Institution
    KAIST, Daejeon
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    1606
  • Lastpage
    1615
  • Abstract
    A 3D vertex processor with a floating-point 4-threaded and 4-issue VLIW architecture and a TnL vertex cache is implemented for mobile multimedia applications in a 0.18mum 4M CMOS process. The proposed architecture efficiently reduces the total energy consumption and achieves 120Mvertices/s with a 2.5GFLOPS datapath using 157mW when operating at 100MHz
  • Keywords
    CMOS integrated circuits; multimedia communication; multiprocessing systems; parallel architectures; parallel machines; 0.18 micron; 100 MHz; 157 mW; 2.5 GFLOPS; 3D vertex processor; CMOS process; TnL vertex cache; floating-point VLIW architecture; mobile multimedia applications; multithreaded VLIW; Bandwidth; Cache memory; Delay; Geometry; Graphics; Ground penetrating radar; Hardware; Mobile handsets; Registers; VLIW;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696215
  • Filename
    1696215
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2569588