Title :
A 40GOPS 250mW massively parallel processor based on matrix architecture
Author :
Nakajima, Masahiro ; Noda, H. ; Dosaka, Katsumi ; Nakata, K. ; Higashida, Manabu ; Yamamoto, Osamu ; Mizumoto, Katsuya ; Kondo, Hiroki ; Shimazu, Y. ; Arimoto, Keisuke ; Saitoh, Kunimasa ; Shimizu, Tsuyoshi
Author_Institution :
Renesas Technol., Itami
Abstract :
The matrix processing engine (MTX) is a massively parallel processor based on the matrix architecture. 40GOPS (16b additions) is achieved at 200MHz clock frequency and 250mW power dissipation. 2048 ALUs and 1Mb SRAM connected by a flexible switching network are integrated in 3.1mm2 using a 90nm CMOS process
Keywords :
CMOS memory circuits; SRAM chips; parallel architectures; parallel memories; switching networks; 1 MByte; 250 mW; 90 nm; ALU; CMOS process; MTX; SRAM; flexible switching network; massively parallel processor; matrix architecture; matrix processing engine; Circuits; Codecs; Energy efficiency; Hardware; Image processing; Image recognition; Joining processes; Random access memory; Registers; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696216
