• DocumentCode
    2569599
  • Title

    A 40GOPS 250mW massively parallel processor based on matrix architecture

  • Author

    Nakajima, Masahiro ; Noda, H. ; Dosaka, Katsumi ; Nakata, K. ; Higashida, Manabu ; Yamamoto, Osamu ; Mizumoto, Katsuya ; Kondo, Hiroki ; Shimazu, Y. ; Arimoto, Keisuke ; Saitoh, Kunimasa ; Shimizu, Tsuyoshi

  • Author_Institution
    Renesas Technol., Itami
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    1616
  • Lastpage
    1625
  • Abstract
    The matrix processing engine (MTX) is a massively parallel processor based on the matrix architecture. 40GOPS (16b additions) is achieved at 200MHz clock frequency and 250mW power dissipation. 2048 ALUs and 1Mb SRAM connected by a flexible switching network are integrated in 3.1mm2 using a 90nm CMOS process
  • Keywords
    CMOS memory circuits; SRAM chips; parallel architectures; parallel memories; switching networks; 1 MByte; 250 mW; 90 nm; ALU; CMOS process; MTX; SRAM; flexible switching network; massively parallel processor; matrix architecture; matrix processing engine; Circuits; Codecs; Energy efficiency; Hardware; Image processing; Image recognition; Joining processes; Random access memory; Registers; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696216
  • Filename
    1696216
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2569599