Circuit design issues in multi-gate FET CMOS technologies

Author

Pacha, Christian ; Von Arnim, Klaus ; Schulz, Thomas ; Xiong, Weize ; Gostkowski, Michael ; Knoblinger, Gerhard ; Marshall, Andrew ; Nirschl, Thomas ; Berthold, Joerg ; Russ, Christian ; Gossner, Harald ; Duvvury, Charvaka ; Patruno, Paul ; Cleavelin, Rin

Author_Institution

Infineon, Munich

fYear

2006

fDate

6-9 Feb. 2006

Firstpage

1656

Lastpage

1665

Abstract

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

Keywords

CMOS integrated circuits; MOSFET; integrated circuit design; operational amplifiers; 1.2 V; 1.5 V; 27 ps; 45 dB; CMOS technologies; FinFET-based Miller OpAmp; circuit design; digital circuit performance; leakage currents; multigate FET; triple-gate FET; CMOS logic circuits; CMOS technology; Circuit optimization; Circuit synthesis; Delay; FETs; FinFETs; Leakage current; Logic devices; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0079-1

Type

conf

DOI

10.1109/ISSCC.2006.1696221

Filename

1696221