A dual-band fractional-N synthesizer for 3G TD-SCDMA

This paper presents a fully integrated CMOS dual-band Sigma-Delta frequency synthesizer with fast lock function for the 3G TD-SCDMA standard transceiver [1]. This single-chip synthesizer integrates the VCO, LO chain, a multi-modulus PLL and a 3^rd order sigma delta modulator on-chip. In order to cover both TD-SCDMA bands with enough margins, an adaptive frequency calibration (AFC) technique is used. The measured VCO tuning range is about 300 MHz (15%) from 1.69 GHz to 2.03 GHz with tuning sensitivity from 15 MHz/V to 30 MHz/V. A fast lock technique is used to reduce the lock time to within 70 mus. The experimental results show -90 dBc/Hz in-band phase noise with the loop bandwidth of 120 kHz, -132dBc/Hz and -136 dBc/Hz out-band phase noise at 3.2 MHz and 4.8 MHz respectively at 1900 MHz carrier frequency. The fractional and reference spurs are all below -80 dBc. The presented synthesizer consumes 20 mA from a single 1.8 V power supply and meets the requirements for the TD-SCDMA application.