Title :
System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV
Author :
Kumagai, Kazuyoshi ; Changqi Yang ; Izumino, H. ; Narita, Naoyuki ; Shinjo, K. ; Iwashita, S. ; Nakaoka, Y. ; Kawamura, Toshihiko ; Komabashiri, H. ; Minato, Tsuneaki ; Arnbo, A. ; Suzuki, Takumi ; Zhenyu Liu ; Yang Song ; Goto, Satoshi ; Ikenaga, Takeshi
Author_Institution :
Syst. Fabrication Technol., Yokohama
Abstract :
System-in-silicon (SiS) is a multi-chip architecture to realize wide bandwidth communication between logic and memory with low power. The application of SiS to H.264/AVC motion estimation is presented. DRAM is integrated with 23.1 Gb/s bandwidth and 1.6pJ/b data transfer efficiency, realizing real-time 1080HDTV processing with 263.1GB/s. The authors present a system-in-silicon architecture with 1024b inter-chip bus to provide high-bandwidth low-power connectivity between logic and memory. The highly parallel architecture also allows low frequency (25MHz) operation while achieving real-time motion estimation for 1080HDTV. The solution achieves the required 23.1 Gb/s bandwidth and associated processing for motion estimation at a power level of 190mW
Keywords :
DRAM chips; high definition television; motion estimation; video coding; 1024 bit; 1080HDTV processing; 190 mW; AVC motion estimation; DRAM chips; H.264 motion estimation; interchip bus; multichip architecture; system-in-silicon architecture; Application specific integrated circuits; Assembly; Automatic voltage control; Design methodology; Fabrication; Motion estimation; Random access memory; Silicon; Testing; Thermal resistance;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696226
