A GaAs buffering circuit LSI for ultra-fast data processing systems

Author

Maeda, T. ; Miyatake, Y. ; Tomonoh, Y. ; Asai, S. ; Ishikawa, M. ; Nakaizumi, K. ; Ohno, Y. ; Ohno, N. ; Furutsuka, T.

Author_Institution

NEC Corp., Kawasaki, Japan

fYear

1988

fDate

6-9 Nov. 1988

Firstpage

139

Lastpage

142

Abstract

A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 mu m. WSi-W bilayer metallization system was used to reduce the gate resistance.<>

Keywords

III-V semiconductors; Schottky gate field effect transistors; buffer circuits; field effect integrated circuits; gallium arsenide; integrated logic circuits; large scale integration; -3.3 V; 1 micron; 1.5 V; 2 ns; 4.8 W; CML compatible interface; GaAs; III-V semiconductors; LDD; MESFET technology; WSi-W bilayer metallization; buffered FET logic; buffering circuit LSI; chip power dissipation; data cycle time; digital IC; gate length; high speed operation; lightly-doped drain; power supply voltage; ultra-fast data processing systems; Circuits; Data processing; FETs; Gallium arsenide; Large scale integration; Optical refraction; Power dissipation; Power supplies; Temperature distribution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE

Conference_Location

Nashville, Tennessee, USA

Type

conf

DOI

10.1109/GAAS.1988.11043

Filename

11043