Title :
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor
Author :
Curran, Brian ; McCredie, Bradley ; Sigal, Leonid ; Schwarz, Egbert ; Fleischer, Bruce ; Chan, Yiu-Hing ; Webber, D. ; Vaden, M. ; Goyal, Ankur
Author_Institution :
IBM, Poughkeepsie, NY
Abstract :
A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases
Keywords :
CMOS integrated circuits; fixed point arithmetic; floating point arithmetic; microprocessor chips; silicon-on-insulator; 4 GHz; 64 bit; 65 nm; CMOS process; POWER6 processor; binary floating-point execution units; fixed-point execution units; silicon-on-insulator; Adders; Circuit simulation; Circuit synthesis; Clocks; Delay; Frequency; Latches; Multiplexing; Performance gain; Pipelines;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696229
