DocumentCode
2569895
Title
A leakage current replica keeper for dynamic circuits
Author
Lih, Yolin ; Tzartzanis, Nestoras ; Walker, William W.
Author_Institution
Fujitsu Labs. of America, Sunnyvale, CA
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
1755
Lastpage
1764
Abstract
A 1T-overhead keeper circuit for dynamic gates replicates the evaluation stack leakage current and thus provides PVT tracking. Implemented in a 90nm CMOS process, the keeper enables design of AND-OR circuits with 30% more legs; 16 to 24 leg dynamic AND-OR circuits are 25 to 40% faster than those with a conventional keeper at the same noise margin. The circuit operation is verified on a 72times1024 3W/4R SRAM
Keywords
CMOS logic circuits; SRAM chips; leakage currents; logic gates; 3-write 4-read SRAM; 90 nm; AND circuits; CMOS process; OR circuits; PVT tracking; dynamic gates; leakage current replica keeper; Analog circuits; CMOS logic circuits; Fingers; Laboratories; Leakage current; Leg; Mirrors; Safety; Temperature; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696232
Filename
1696232
Link To Document