DocumentCode
2569913
Title
An on-chip delay- and skew-insensitive multicycle communication scheme
Author
Caputa, P. ; Stevenson, Cory
Author_Institution
Linkoping Univ.
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
1765
Lastpage
1774
Abstract
A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs
Keywords
CMOS integrated circuits; delays; integrated circuit design; integrated circuit interconnections; synchronisation; 0.18 micron; 5.4 mm; CMOS process; data synchronization; data-clock skew; global clock skew; multicycle communication; on-chip global wire delays; synchronous latency-insensitive design; CMOS process; Clocks; Communication system control; Delay; Design methodology; Process design; Signal design; Signal processing; Synchronization; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696233
Filename
1696233
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