A parallel serial filtering mixed advanced ID interpolation architecture for AVS

This paper presents an advanced ID interpolation architecture for AVS video coding standard. Previous approaches have demerit of low data throughput. The proposed design parallel filters the horizontal data and serial filters the vertical data, thus greatly improve the throughput. Experimental result shows it outperforms conventional designs in processing cycle and chip area. The prototype design costs 26.2 K gates when synthesized at 108 MHz using 0.18 mum CMOS technology.