A Novel reconfigurable VLSI architecture for motion estimation

A new reconfigurable multi-BMA VLSI architecture was proposed to select different levels of trade-off between video quality, computing complexity and power for power aware applications. The architecture can reuse the smaller blocks´ SADs to calculate 41 motion vectors of a 16times16 block in parallel for H.264´s VBSME. TSMC 0.18 um CMOS technology was adopted and the circuit´s power consumption can be changed between 13.8 and 247 mW with the typical algorithms. Under a clock frequency of 157 Mhz, the architecture allows the real-time processing of VGA at 30 fps with FS in a search range [-16, +15] at the high level.