Title :
GaAs 8-CH 16-bit word-generator/error-detector operating at 3-Gb/s data rate
Author :
Takada, Tohru ; Hirayama, Masahiro
Author_Institution :
LSI Lab., NTT, Kanagawa, Japan
Abstract :
An 8-channel 16-bit word-generator/1-channel 16-bit error detector operating at up to 3 Gb/s was developed using specially designed GaAs LSIs that include 750 effective gates (3132 devices). Two technologies, LSCFL (low-power source-coupled FET logic) and FG-SAINT (flat-gate self-aligned implantation for n+ layer technology), have been adopted for the LSI circuit design and fabrication process, respectively. The developed generator/detector, capable of either SCFL (V/sub H/=0 V, V/sub L/=0.8 V) or ECL (emitter-coupled logic) I/O interface, consists of nine GaAs LSIs, GaAs discrete FETs for high-speed circuits, and Si ICs for low-speed circuits. Rise time, fall time, and jitter of generator outputs are 41, 49 (20-80%) and 33 ps, respectively. Skew among the eight channel outputs is less than 30 ps.<>
Keywords :
III-V semiconductors; digital instrumentation; digital integrated circuits; error detection; field effect integrated circuits; gallium arsenide; integrated logic circuits; large scale integration; signal generators; 3 Gbit/s; 30 to 49 ps; ECL I/O interface; FG-SAINT; GaAs; III-V semiconductors; LSCFL; LSI circuit design; LSI devices; SCFL I/O interface; digital ICs; eight channel configuration; error-detector; fabrication process; flat-gate; low-power source-coupled FET logic; n+ layer technology; self-aligned implantation; word-generator; Circuit synthesis; Detectors; FETs; Fabrication; Gallium arsenide; Jitter; Large scale integration; Logic circuits; Logic design; Logic devices;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE
Conference_Location :
Nashville, Tennessee, USA
DOI :
10.1109/GAAS.1988.11045
