Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC

The latest video coding standard H.264/AVC covers a wide range of applications from QCIF to HDTV. In case of HDTV, subsampling technique is widely adopted to reduce hardware cost with little video quality degradation. Moreover, experiments show that contribution of small inter search modes to video quality is trivial so that mode reduction can help to further reduce hardware cost. This paper proposes a cost efficient Propagate Partial SAD architecture for HDTV application. The highly pipelined feature of proposed architecture makes it robust to high speed impact. Compared with widely used SAD Tree structure, the proposed cost efficient structure which adopts subsampling and inter search mode reduction can reduce averagely 23.88% hardware cost with negligible video quality loss. With TSMC 0.18 mum CMOS 1P6M standard cell library, the maximum clock speed of this design is 233 MHz in worst work condition (1.62, 125degC).