A high-performance VLSI architecture for CABAC decoding in H.264/AVC

Author

Bingbo, Li ; Ding, Zhang ; Jian, Fang ; Lianghao, Wang ; Ming, Zhang

Author_Institution

Zhejiang Univ., Hangzhou

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

790

Lastpage

793

Abstract

A mixed hardware/software architecture for CABAC decoding in H.264/AVC is proposed in this paper. For the purpose of flexibility, ctxldx calculation process is implemented by software, while others are implemented by hardware. An optimized parallel decoding architecture that allows decoding two binary symbols at one clock cycle is designed to enhance overall decoding performance. An efficient scheme of accessing context models is presented. Experimental results show that the proposed architecture improves the decoding performance by 20% compared to conventional scheme. The proposed design can achieve HDTV 1080i video processing requirement when operated at 140 MHz.

Keywords

VLSI; decoding; hardware-software codesign; parallel architectures; video coding; CABAC decoding; H.264/AVC; binary symbols; ctxldx calculation process; high-performance VLSI architecture; mixed hardware/software architecture; one clock cycle; optimized parallel decoding architecture; Automatic voltage control; Clocks; Computer architecture; Context modeling; Decoding; Design optimization; HDTV; Hardware; Software architecture; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1132-0

Electronic_ISBN

978-1-4244-1132-0

Type

conf

DOI

10.1109/ICASIC.2007.4415749

Filename

4415749