• DocumentCode
    2570182
  • Title

    A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration

  • Author

    Gupta, Manoj ; Song, Bang-Sup

  • Author_Institution
    California Univ., San Diego, CA
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    1922
  • Lastpage
    1931
  • Abstract
    A 1.8GHz wideband fractional-N synthesizer achieves the phase noise of an integer-N PLL using a noise-cancellation DAC calibrated with an adaptive LMS spur correlation technique. It exhibits in-band and integrated phase noises of -98dBc/Hz and 0.8deg, respectively. The chip in 0.18mum CMOS occupies 2mm2, and consumes 29mW at 1.8V
  • Keywords
    CMOS integrated circuits; UHF frequency convertors; UHF integrated circuits; digital-analogue conversion; frequency synthesizers; phase locked loops; phase noise; 0.18 micron; 1.8 GHz; 1.8 V; 29 mW; CMOS fractional-N frequency synthesizer; CMOS technology; DAC gain calibration; digital-analogue conversion; integrated phase noise; noise-cancellation DAC; phase locked loops; spur correlation; Calibration; Filters; Frequency synthesizers; Least squares approximation; Linearity; Noise shaping; Phase frequency detector; Phase locked loops; Voltage; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696250
  • Filename
    1696250
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2570182