DocumentCode

2570237

Title

Clip: An Optimizing Layout Generator For Two-dimensional Cmos Cells

Author

Gupta, Avaneendra ; Hayes, John P.

Author_Institution

University of Michigan

fYear

1997

fDate

9-13 June 1997

Firstpage

452

Lastpage

455

Keywords

CMOS technology; Circuit synthesis; Circuit testing; Computer architecture; Laboratories; Linear programming; Minimization; Routing; Semiconductor device modeling; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the 34th

Conference_Location

Anaheim, CA, USA

ISSN

0738-100X

Print_ISBN

0-7803-4093-0

Type

conf

DOI

10.1109/DAC.1997.597190

Filename

597190