DocumentCode
2570377
Title
A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction
Author
Snoeij, M.F. ; Theuwissen, A. ; Makinwa, K. ; Huijsing, J.H.
Author_Institution
Delft Univ. of Technol.
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
2014
Lastpage
2023
Abstract
A CMOS imager with a column-level ADC uses a dynamic column FPN reduction technique. This technique requires 5 extra switches per column and minimal digital overhead at the chip level while reducing the perceptual effect of column FPN. Measurements show that the prototype makes a column FPN of plusmn0.67% nearly invisible
Keywords
CMOS image sensors; analogue-digital conversion; integrated circuit noise; CMOS imager; analog-to-digital converters; column level ADC; dynamic column FPN reduction technique; CMOS image sensors; CMOS process; CMOS technology; Energy consumption; Image quality; Pixel; Prototypes; Semiconductor device measurement; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696260
Filename
1696260
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