Title :
High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor
Author :
Nitta, Yoshikazu ; Muramatsu, Yoshinori ; Amano, Kiyotaka ; Toyama, Takayuki ; JunYamamoto ; Mishina, Koji ; Suzuki, Atsushi ; Taura, Tadayuki ; Kato, Akihiko ; Kikuchi, Masaru ; Yasui, Yukihiro ; Nomura, Hideo ; Fukushima, Noriyuki
Author_Institution :
Sony, Atsugi
Abstract :
A progressive 1/1.8-inch 1920times1440 CMOS image sensor with a column-inline dual CDS architecture uses a 0.18mum CMOS process. This sensor implements digital double sampling with analog CDS on a column parallel ADC. Random noise is 5.2e-rms and the DR is 68dB at 180frames/s(6.0Gb/s). FPN is <0.5e-rms without the correction circuit
Keywords :
CMOS image sensors; analogue-digital conversion; integrated circuit noise; random noise; 0.18 micron; CMOS image sensor; CMOS process; analog CDS; column parallel ADC architecture; column-inline dual CDS architecture; high-speed digital double sampling; low-noise active pixel sensor; random noise; Circuit noise; Clocks; Computational Intelligence Society; Counting circuits; Decoding; Image quality; Image sensors; Logic arrays; Phase locked loops; Sampling methods;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696261
