The decoder of trellis code implemented by CMOS analog circuits

This paper analyses some circuits of the analog decoder of (5,2,3) trellis code, which is implemented by CMOS analog circuits. The decoding performance of the analog decoder is given. Simulation results show that the analog decoder decreases at least one decimal power consumption and chip area at the same bit rate, compared with the digital decoder. For the Turbo code and LDPC, if they are decoded by digital circuits, the quantity of the transistors and the computing power will be very great. If we use analog decoder, the power consumption and the chip area will be very small.