Title :
Design and implementation of crypto-based interleaver for viterbi encoder and decoder using turbo codes
Author :
Hemant, Koka ; Hamsavahini ; Upadhyay, Pawan ; Akhter, Shamim
Author_Institution :
Jaypee Inst. of Inf. Technol., Noida
Abstract :
-In this paper, we have presented the hardware design implementation of crypto-based Viterbi encoder and decoder using turbo codes. Our design is based on 2/3 bit rate for a constraint length of 3. The turbo encoder has been designed with shift register, modulo-2 adder, TDES (triple-data encryption standard) interleaver. Viterbi decoder section includes convolutional decoder and TDES interleaver and TDES de-interleaver. The results of simulation are obtained from Modelsim 5.8c and the design has been implemented on Spartan2 FPGA using Xilinx 5.1i. The estimated operating frequency for our design was 94.5 MHz which is similar to the existing Block Interleaver using the synthesis tool Leonardo Spectrum 2004.1b.
Keywords :
Viterbi decoding; convolutional codes; cryptography; field programmable gate arrays; interleaved codes; turbo codes; Spartan2 FPGA; TDES; Viterbi decoder; Viterbi encoder; convolutional decoder; crypto-based interleaver; modulo-2 adder; shift register; triple-data encryption standard; turbo codes; Bit rate; Convolutional codes; Cryptography; Decoding; Field programmable gate arrays; Frequency estimation; Hardware; Shift registers; Turbo codes; Viterbi algorithm; Cryptography; DES; De-Interleaver; Interleaver; TDES; Viterbi Encoder and Decoder;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415778
