• DocumentCode
    2570873
  • Title

    ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS

  • Author

    Ker, Ming-Dou ; Chang, Wei-Jen ; Wang, Chang-Tzu ; Chen, Wen-Yi

  • Author_Institution
    Nat. Chiao-Tung Univ., Hsin-Chu
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    2230
  • Lastpage
    2237
  • Abstract
    An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13mum CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme
  • Keywords
    CMOS integrated circuits; electrostatic discharge; low-power electronics; 0.13 micron; 1.2 V; 2.5 V; ESD protection; electrostatic discharge; four-mode ESD stress; low-voltage devices; low-voltage thin-oxide CMOS; mixed-voltage I/O interfaces; power-rail ESD clamp circuit; CMOS process; CMOS technology; Circuits; Clamps; Electrostatic discharge; Power supplies; Protection; Stress; Variable structure systems; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696284
  • Filename
    1696284
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2570873