Title :
Neurons to Silicon: Implantable Prosthesis Processor
Author :
O´Driscoll, Stephen ; Meng, Teresa ; Shenoy, Krishna ; Kemere, Caleb
Author_Institution :
Stanford Univ., CA
Abstract :
A processor architecture for neural prosthesis control is described. It implements real-time neural decoding from a permanently implanted electrode array to reduce the data rate from 80Mb/s to 20b/s, minimizing the wireless communication requirements. The neural signals are digitized by a 100-channel 100kS/s adaptive-resolution ADC array consuming 1muW per channel
Keywords :
analogue-digital conversion; biomedical electrodes; microprocessor chips; neural chips; prosthetics; adaptive-resolution ADC array; analog-to-digital converters; implantable prosthesis processor; implanted electrode array; neural decoding; neural prosthesis control; neural signals; processor architecture; wireless communication; Data mining; Energy consumption; Energy resolution; MIM capacitors; Neural prosthesis; Neurons; Parasitic capacitance; Prosthetics; Signal processing; Silicon;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696287
