A high-performance VLSI architecture for variable block size motion estimation

Variable block size motion estimation (VBSME) is a video coding technique which improves video distortion, provides more accurate predictions, reduces video coding data, and increases the utilization of network bandwidth. This paper presents a high-performance VLSI architecture for VBSME which can be applied to the full search block matching algorithm. Our proposed architecture uses pipelined designs to balance the execution time of each stage in order to increase the performance. Furthermore, our design employs parallelism to improve the throughput and facilitate lower computation time. The implementation shows that our design outperforms many previously proposed designs with moderate chip area cost.