• DocumentCode
    2571050
  • Title

    A hardware approach to reconfigurable lossless real-time tracer

  • Author

    Si-liang, Hua ; Lei, Shi ; Jun, Pang ; Tie-jun, Zhang ; Dong-hui, Wang ; Chao-huan, Hou

  • Author_Institution
    Chinese Acad. of Sci., Beijing
  • fYear
    2007
  • fDate
    22-25 Oct. 2007
  • Firstpage
    986
  • Lastpage
    989
  • Abstract
    Address tracing at speed is essential to the debugging or analyzing software programs in a complex system. However, the generation rate and the size of real-time program traces are so huge that real-time program tracing is often infeasible without proper hardware support. In this paper, we present a reconfigurable lossless real-time tracer with three parts. A synthesizable RTL code for the proposed hardware is constructed and the tracer is integrated with a microprocessor. Hardware cost and speed is analyzed and typical programs are used to measure the compression results. The results show that the reconfigurable tracer is capable of real-time compression and outputting the compressed data less than 1 bit per cycle on average at 266 MHz with 172963 mum2 area in 0.18 mum CMOS process.
  • Keywords
    CMOS digital integrated circuits; data compression; microprocessor chips; program debugging; reconfigurable architectures; tracers; CMOS digital integrated circuits; RTL code; frequency 266 MHz; reconfigurable lossless real-time tracer; size 0.18 mum; software analyzing; software debugging; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2007. ASICON '07. 7th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4244-1132-0
  • Electronic_ISBN
    978-1-4244-1132-0
  • Type

    conf

  • DOI
    10.1109/ICASIC.2007.4415798
  • Filename
    4415798