DocumentCode :
2571064
Title :
Performance of Triplet Based Interconnection Strategy for Multi-Core On-Chip Processors
Author :
Khan, Haroon-ur-Rashid ; Feng, Shi ; Xinli, Jia ; Ziru, Bai
Author_Institution :
Dept. of Comput. Sci. & Eng., Beijing Inst. of Technol., Beijing, China
fYear :
2009
fDate :
25-27 June 2009
Firstpage :
163
Lastpage :
170
Abstract :
We have entered the era of many-core processors and complex SoCs, where on-chip interconnection networks play a dominant role in determining the performance, power, and ultimately cost of a system. Therefore, interconnection strategy that supports efficient communication between IP blocks is essential. Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. We propose a new criterion in performance evaluation that is based on the concept of group locality in an interconnection network, the ldquolower layer complete connectrdquo. Our proposed criterion depicts how completely a processing node is connected to all its neighbors. In this paper we evaluate TriBA, a class of direct interconnection network (DIN), for multi-core on-chip interconnection architecture. TriBA is compared with 2D mesh as static interconnection networks for VLSI implementation. The criteria of evaluation are enumerated from two orthogonal view points, viz., computational speed and physical layout. We conclude that TriBA has the potential to have significantly better performance as an on-chip interconnection network for future MPSoC systems.
Keywords :
VLSI; microprocessor chips; multiprocessor interconnection networks; system-on-chip; 2D mesh; IP blocks; MPSoC systems; VLSI implementation; direct interconnection network; multicore on-chip interconnection architecture; multicore on-chip processors; on-chip interconnection networks; system-on-chip; triplet based interconnection strategy; Computer architecture; Costs; Multiprocessor interconnection networks; Network topology; Network-on-a-chip; Physics computing; Power system interconnection; Power system modeling; System-on-a-chip; Very large scale integration; interconnection; locality; multi-core; performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computing and Communications, 2009. HPCC '09. 11th IEEE International Conference on
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-4600-1
Electronic_ISBN :
978-0-7695-3738-2
Type :
conf
DOI :
10.1109/HPCC.2009.81
Filename :
5166990
Link To Document :
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