• DocumentCode
    2571142
  • Title

    A design approach for predictable and efficient multi-core processor for avionics

  • Author

    Agrou, Hicham ; Gatti, Marc ; Sainrat, Pascal ; Toillon, Patrice

  • fYear
    2011
  • fDate
    16-20 Oct. 2011
  • Firstpage
    1
  • Lastpage
    32
  • Abstract
    Academic Predictable Multi-core Processor: MERASA & PRET processors COTS architecture: IBM™ Cell, Freescale™´s MPC8641D & QorIQ Platform Local memories (scratchpads & caches): • Best cache policy (for analyzability) • Cache Analysis (optimization to reduce cache pollution) • Shared Cache Strategy to reduce interferences Interconnect Element: • Shared Bus (bounding access time) • Ring protocols • CoreNet, & Data Path Accelerator Architecture
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Avionics Systems Conference (DASC), 2011 IEEE/AIAA 30th
  • Conference_Location
    Seattle, WA, USA
  • ISSN
    2155-7195
  • Print_ISBN
    978-1-61284-797-9
  • Type

    conf

  • DOI
    10.1109/DASC.2011.6096286
  • Filename
    6096286
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2571142